Rolf Drechsler (http://www.rolfdrechsler.de/) received the Diploma and Dr. phil. nat. degrees in computer science from the Johann Wolfgang Goethe University in Frankfurt am Main, Germany, in 1992 and 1995, respectively. He worked at the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and at the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since October 2001, Rolf Drechsler is Full Professor and Head of the Group of Computer Architecture, Institute of Computer Science, at the University of Bremen, Germany. In 2011, he additionally became the Director of the Cyber-Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. He is an IEEE Fellow.
Daniel Große received the Dr.-Ing. degree in computer science from the University of Bremen in 2008. He remained as a Post-Doctoral Researcher with the Group of Computer Architecture, University of Bremen. In 2010, he was a substitute Professor for computer architecture with Albert-Ludwigs University, Freiburg im Breisgau, Germany. From 2013 to 2014, he was the CEO of the EDA start-up solvertec focusing on automated debugging techniques. Since 2015, he has been a Senior Researcher with the University of Bremen and at the German Research Center for Artificial Intelligence (DFKI), and also the Scientific Coordinator of the Graduate School of System Design, funded within the German Excellence Initiative. Since July 2020, he is a full professor at the Johannes Kepler University Linz, Austria, where he is the head of the Institute for Complex Systems. His current research interests include verification, virtual prototyping, debugging, and synthesis. He published over 140 papers in peer-reviewed journals and conferences in the above areas. Dr. Großeserved in program committees of numerous conferences, including ASP-DAC, DAC, DATE, ICCAD, CODES+ISSS, FDL, and MEMOCODE. He received best paper awards at FDL 2007, DVCon Europe 2018, ICCAD 2018, and FDL 2020. He is an IEEE Senior Member.